The hardware design process is under increasing pressure—greater complexity, tighter schedules, and limited engineering resources. High-Level Synthesis (HLS) has proven to dramatically improve productivity and reduce complexity, especially in datapath-centric designs. But what about control logic?
While many engineers are familiar with the benefits of HLS for datapath, there’s often less clarity around how it handles complex control flow, or how to effectively approach it at a higher level of abstraction. That’s exactly the focus of this technical webinar.
Join us for a deep-dive session on designing and verifying control logic using high-level design methodologies. We’ll show how Rise Design Automation’s multi-language, multi-abstraction toolchain—supporting C++, SystemC, and SystemVerilog—works in conjunction with generative AI to help engineers express, optimize, and verify control behavior without always having to hand-code state machines in RTL.
Whether you’re evaluating if your current project is a good fit for high-level design, or looking to extend your existing HLS methodology, this session delivers practical, engineer-first insights that you can apply immediately.
Rise Design Automation: An Introduction
Get a technical overview of the Rise toolchain and how it addresses today’s hardware design challenges through multi-language, mixed-abstraction support. Learn how it differs from traditional HLS approaches and where it fits best in modern design flows and various customer case studies.
High-Level Coding for Control Logic
This session focuses on describing complex control logic using high-level constructs. We’ll start with a brief overview of how HLS works, what it does, and how it fits into the design process.
While the Rise toolchain supports C++, SystemC, and SystemVerilog, this webinar will use SystemVerilog to implement the featured design example: a Tiled Matrix Multiplication Compute Engine with built-in DMA control, bus interfaces, and on-chip buffering. This example will be used to walk through key concepts, illustrating how control is modeled at a high level and how the tool automatically generates the corresponding FSMs, handshake logic, and timing control.
You’ll learn how to:
This section is ideal for engineers who want to write high-level control logic that translates into clean, efficient hardware—without sacrificing clarity or maintainability.
Early and Accurate Performance Analysis+HL Verification
See how high-level models can be used for early performance analysis and functional verification—delivering simulation speeds 30x or more faster than RTL. This session will also preview how to run simulations and close code coverage from high-level through to RTL, using the same DMA + Neural Network design example.
Live Demonstration
Watch a hands-on walkthrough of the compute engine code example through the Rise High-Level toolchain, including editing, synthesis, verification, and debugging. We’ll step through key concepts covered in the session and show how they apply in a real design.
Hardware engineers, architects, verification engineers, and engineering managers looking to improve productivity, maintainability, and scalability in their design process.
Note: While not required, prior experience with RTL design will help attendees get the most out of this highly technical session.
Mike Fingeroff, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation, Mike has specialized in High-Level Synthesis (HLS), focusing on machine learning and early performance modeling using SystemVerilog, SystemC, and MatchLib. He is the author of The High-Level Synthesis Blue Book, and his expertise includes C++, SystemC, and video and wireless algorithms. 
Ellie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries, she has held diverse roles in engineering, applications engineering, technical marketing, product management, and senior leadership, specializing in driving business growth through strategic marketing.
