Search
Close this search box.
Contact Us

1-hr Technical Webinar

Presented in partnership with Rise Design Automation and SemiWiki

SystemVerilog at the Core: Scalable Verification and Debug in HLS

Guest speaker, verification methodology specialist
and architect, Mark Glasser

Live: 9am PST, Oct 08, 2025

Leverage your existing SystemVerilog and mixed-language verification methodologies in an HLS flow — enabling consistent verification from high level through RTL, without translation or duplication

Verification has long been the bottleneck in hardware design. With High-Level Synthesis (HLS), many teams discover an unexpected benefit: verification can start earlier, run significantly faster, and make debug easier.

While raising abstraction dramatically improves productivity, most HLS flows begin in C++ or SystemC. Design teams are comfortable at RTL, and verification teams often rely on SystemVerilog/UVM. This disconnect can lead to duplicated effort, delayed bug discovery, and complex debug.

Rise Design Automation is unifying design and verification teams across language and abstraction boundaries. By fully supporting C++ and SystemC in existing HLS flows, and uniquely enabling native SystemVerilog with true mixed-language synthesis and verification, Rise delivers the benefits of high-level design while easing adoption and managing risk.

This webinar opens with a special introduction by Mark Glasser, verification architect and methodology expert. Mark will share his perspective and lessons learned on the value of raising abstraction for both verification and design. While Rise supports multiple verification methodologies and languages, the remainder of the session will focus on how SystemVerilog can be applied consistently from HLS through RTL — enabling reuse of UVM and familiar infrastructures, while simplifying debug through powerful automation and HL–RTL correlation.

What You'll Learn

In this deep-dive session, you’ll see how Rise DA helps you:

  • Understand untimed and loosely timed SystemVerilog for high-level synthesis
 
  • Apply SystemVerilog methodologies from high-level models through RTL
 
  • Use UVM to drive both behavioral and RTL models, enabling self-checking and result comparison
 
  • Autogenerate adapters between languages and abstractions for mixed-abstraction and mixed-language simulations
 
  • Debug with HL↔RTL correlation, transaction-level waveforms, and RTL signal visibility
 
  • Enhance debug with RTL line-number annotation, synthesized asserts/covers, and $display support

 

Whether you’re evaluating HLS or integrating it deeply into your flow, this webinar offers practical techniques to accelerate verification and debug.

Live Demonstration

Follow a walkthrough of a design example in the Rise DA flow. See how verification begins at the high level, carries through RTL, and maintains methodology reuse and debug continuity

Who Should Attend:

Verification engineers, hardware designers, architects, and methodology leads who want to:

  • Boost design and verification productivity
  • Catch bugs earlier in the flow (up to 95% before RTL)
  • Achieve 30×–100× faster simulation than RTL-only flows
  • Leverage SystemVerilog/UVM expertise in an HLS context
  • Simplify debug while increasing verification confidence

Registration Form

Please enable JavaScript in your browser to complete this form.
Name
This could be specifics on things you want to make sure you learn or that we include. It helps to know in advance so that we could either email you directly or include in our live presention.

Speakers

Mark GlasserMark Glasser, is a distinguished verification architect and methodologist with over 30 years of experience. He co-invented the Open Verification Methodology (OVM) and Universal Verification Methodology (UVM), which have shaped modern semiconductor verification practices. Author of The OVM Cookbook (2009) and Next Level Testbenches: Design Patterns in SystemVerilog and UVM (2024), Mark now consults with Paradigm Works to help teams advance their verification capabilities.

Mike Fingeroff, Chief of High-Level Synthesis, Rise Design AutomationMike Fingeroff, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation, Mike has specialized in High-Level Synthesis (HLS), focusing on machine learning and early performance modeling using SystemVerilog, SystemC, and MatchLib. He is the author of The High-Level Synthesis Blue Book, and his expertise includes C++, SystemC, and video and wireless algorithms.

Ellie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries, she has held diverse roles in engineering, applications engineering, technical marketing, product management, and senior leadership, specializing in driving business growth through strategic marketing.
Linkedin Youtube

Products

Company

Get In Touch