To access this Lunch and Learn On-Demand you will need to register. Once you register, we will send you an email with a link and password for you to immediately access the content. The password can be reused to view the content anytime.
This Lunch & Learn offers an in-depth look at Rise Design Automation tools and illustrates how high-level design and early verification techniques can bring value to your projects. No prior experience with high-level design is necessary, but familiarity with hardware design and RTL synthesis is recommended.
Some key takeaways you can expect:
** Rise Design Automation Overview – Introduction to the tools, use cases, methodologies, and project value of raising the abstraction beyond RTL with Rise.
** SystemVerilog – Technical details of how to use SystemVerilog for high-level design – highlighting both “loosely-timed” and “untimed” SystemVerilog.
** Handling Control and Data Flow – Learn practical approaches to optimizing control and data paths to meet timing and performance requirements without adding unnecessary complexity.
** Applying Design Space Exploration – Explore design configurations by adjusting loop unrolling, pipelining, and scheduling to optimize power, performance, and area—while gaining early insights into trade-offs.
** Improving Early Verification – How to integrate verification earlier in the design process to detect bugs faster and reduce the risk of late-stage rework.
** Real-World Use Cases – See how high-level design techniques are used to efficiently build a high-performance compute accelerator for applications like machine learning, DSP, and video/image processing.
** Learn how collaboration between system architects, RTL designers, and verification engineers speeds up development and delivers more reliable hardware.
** Design Engineers looking to improve control paths, data flow, and performance, while adopting new methods gradually and with minimal risk.
** Verification Engineers looking to implement earlier, more efficient verification processes to minimize risk and accelerate timelines, without overhauling their current flows.
** Project Leads managing trade-offs in timelines, power, performance, and area, while ensuring smooth integration of new techniques into existing processes.
** System Architects looking to model, explore, and validate architectural decisions early, focusing on performance, power, and area trade-offs without late-stage surprises.
Mike Fingeroff, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation, Mike has specialized in High-Level Synthesis (HLS), focusing on machine learning and early performance modeling using SystemVerilog, SystemC, and MatchLib. He is the author of The High-Level Synthesis Blue Book, and his expertise includes C++, SystemC, and video and wireless algorithms. 
Allan Klinck, Co-Founder
Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies, helping teams enhance efficiency and performance in modern, complex designs. 
Ellie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries, she has held diverse roles in engineering, applications engineering, technical marketing, product management, and senior leadership, specializing in driving business growth through strategic marketing. 