AI-Driven Architectural Exploration with Real Physical-Design Feedback — from high-level models through implementable RTL and physically correlated PPA.
As hardware designs become more complex, architectural exploration is increasingly critical to delivering differentiated silicon. Teams often develop promising new architectures, only to discover late in the design cycle that physical implementation is too costly or fails to meet specifications. This challenge grows even more acute as designers integrate new accelerators — video, audio, ML, or custom datapaths — causing the search space to expand rapidly.
AI-based automation can help, but only when each exploration trial produces cost metrics (area, timing, power) that are both fast and credible. Traditional parameter sweeps are too slow. Full physical analysis is too expensive. And without correlation to real implementation costs, AI-guided exploration simply delivers the wrong answers faster.
Rise Design Automation and Precision Innovations are partnering to change this dynamic. Together, they enable fast, accurate, physically aware exploration loops — ideal for reinforcement learning, iterative refinement, and high-volume experimentation.
Rise provides 10× faster HLS with correlation within a few percent of customer production RTL synthesis results. Precision’s OpenROAD-based RTL→GDSII flow adds production-grade physical estimation with strong area and timing accuracy, validated down to advanced nodes (including 2–3nm).
Combined, this integrated flow supports rapid exploration from high-level C++/SystemC/SystemVerilog through synthesized RTL to physically correlated PPA — enabling hundreds or thousands of trials without licensing barriers.
This session will demonstrate how Rise + Precision deliver the fast, accurate feedback required for AI-driven architectural exploration, and how you can incorporate these capabilities directly into your own design flow.
In this technical deep dive, you’ll see how Rise + Precision help you:
See a complete exploration loop from high-level behavioral model through Rise HLS, into Precision’s OpenROAD-based physical estimator, with AI-guided refinement of architectural choices driven by real PPA feedback.
Hardware architects, design engineers, verification leads, and research teams who want to:
Whether you’re adding a new accelerator to an SoC or exploring ML-driven design automation, this session provides a practical foundation for leveraging Rise + Precision.
Tom Spyrou, CEO of Precision Innovations and a recognized leader in electronic design automation with more than 25 years of experience spanning physical design, performance optimization, and advanced-node implementation. Before founding Precision, Tom helped lead the development of the OpenROAD project at UCSD, transforming it into the industry’s most advanced open-source RTL-to-GDSII flow. His work focuses on delivering fast, accurate, and scalable physical design technology for both commercial and research applications, enabling design teams to explore architectures and achieve PPA closure with unprecedented speed and transparency.
Mike Fingeroff, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation, Mike has specialized in High-Level Synthesis (HLS), focusing on machine learning and early performance modeling using SystemVerilog, SystemC, and MatchLib. He is the author of The High-Level Synthesis Blue Book, and his expertise includes C++, SystemC, and video and wireless algorithms.
Ellie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries, she has held diverse roles in engineering, applications engineering, technical marketing, product management, and senior leadership, specializing in driving business growth through strategic marketing. 